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Data Sheet
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
June 1997
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.1
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Features: Single 3.0-Volt Read and Write Operations CMOS SuperFlash EEPROM Technology Endurance: 100,000 Cycles (typical) Greater than 100 years Data Retention Memory Organization: 512K x 8 Sector Erase Cap ability: 256 bytes per Sector Low Power Consumption: Active Current: 10 mA (typical) Standby Current: 5 A (typical) Fast Sector Erase/Byte Program Operation Byte Program Time: 35 s (typical) Sector Erase Time: 2 ms (typical) Complete Memory Rewrite: 20 sec (typical) Fast Access Time: 200 and 250 ns Product Description The 28LF040 is a 512K x 8 (bits) CMOS sector erase, byte program EEPROM. The 28LF040 is manufactured using SST's proprietary, high pe rformance CMOS SuperFlash EEPROM Technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternative a pproaches. The 28LF040 erases and programs with a 3.0 volt only power supply. (V : 3.0V to CC 3.6V) The 28LF040 conforms to JEDEC standard pinouts for byte wide memories and is compatible with existing industry standard EPROM, flash EPROM and EEPROM pinouts. Featuring high performance programming, the 28LF040 typically byte programs in 35 s. The 28LF040 typically sector erases in 2 ms. Both program and erase times can be optimized using interface features such as Toggle bit or Data# Polling to indicate the completion of the write c ycle. To protect against an inadvertent write, the 28LF040 has on chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the 28LF040 is offered with a guaranteed sector 4 3 endurance of 10 and 10 cycles. Data retention is rated greater than 100 years. The 28LF040 is best suited for applications that require reprogrammable nonvolatile mass storage of program, configuration, or data memory. For all system applications, the 28LF040 significantly mi proves performance and reliability, while lowering Latched Address and Data Hardware and Software Data Protection 7-Read-Cycle-Sequence Software Data Protection End of Write Detection Toggle Bit Data# Polling TTL I/O Compatibility Packages Available 40-Pin TSOP (10 mm x 20 mm) 32-Pin TSOP (8 mm x 20 mm) 32-Pin PLCC 32-Pin PDIP
power consumption when compared with floppy diskettes or EPROM approaches. EEPROM tec hnology makes possible convenient and economical updating of codes and control pr o grams on-line. The 28LF040 improves flexibility, while lowering the cost of program and configur a tion storage application. Figure 1 shows the functional blocks of the 28LF040. Figures 2A, 2B, and 3 show the pin a ssignments for the 40 pin TSOP, 32 pin TSOP, 32 pin PDIP, and 32 pin PLCC packages. Pin d escription and operation modes are described in Tables 1 through 4. Device Operation Commands are used to initiate the memory o peration functions of the device. Commands are written to the device using standard microproce ssor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whic hever occurs first. Note, during the software data protection sequence the address are latched on the rising edge of OE# or CE#, whichever occurs first. Command Definitions Table 3 contains a command list and a brief summary of the commands. The following is a detailed description of the operations initiated by each command.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.2
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Sector_Erase Operation The Sector_Erase operation erases all bytes within a sector and is initiated by a setup co mmand and an execute command. A sector contains 256 bytes. This sector erasability e nhances the flexibility and usefulness of the 28LF040, since most applications only need to change a small number of bytes or sectors, not the entire chip. The setup command is performed by writing 20H to the device. The execute command is performed by writing D0H to the device. The erase operation begins with the rising edge of the WE# or CE#, whichever occurs first and terminates automati cally by using an internal timer. The end of Erase can be determined using either Data# Polling, Toggle Bit, or Successive Reads detection met h ods. See Figure 9 for timing wav eforms. The two-step sequence of setup command fo llowed by an execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased. Sector_Erase Flowchart Description Fast and reliable erasing of the memory contents within a sector is accomplished by following the sector erase flowchart as shown in Figure 18. The entire procedure consists of the execution of two commands. The Sector_Erase operation will te rminate after a maximum of 4 ms. A Reset command can be executed to terminate the erase operation; however, if the erase operation is te rminated prior to the 4 ms time-out, the sector may not be fully erased. An erase command can be reissued as many times as necessary to complete the erase operation. The 28LF040 cannot be "overerased". Chip_Erase Operation The Chip_Erase operation is initiated by a setup command (30H) and an execute command (30H). The Chip_Erase operation allows the entire array of the 28LF040 to erase in one operation, as o pposed to 2048 sector erase operations. Using the Chip_Erase operation will minimize the time to rewrite the entire memory array. The Chip_Erase operation will terminate after a maximum of 20 ms. A Reset command can be executed to term inate the erase operation; however, if the erase operation is terminated prior to the 20 ms timeout, the Chip may not be completely erased. If an erase error occurs an erase command can be er issued as many times as necessary to complete the erase operation. The 28LF040 cannot be "overerased". (See Figure 8) Byte_Program Operation The Byte_Program operation is initiated by writing the setup command (10H). Once the program setup is performed, programming is executed by the next WE# pulse. See Figures 5 and 6 for ti ming waveforms. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first, and begins the program operation. The program operation is terminated automatically by an internal timer. See Figure 16 for the programming flowchart. The two-step sequence of a setup command fo llowed by an execute command ensures that only the addressed byte is programmed and other bytes are not inadvertently programmed. The Byte_Program Flowchart Description Programming data into the 28LF040 is acco mplished by following the Byte_Program flowchart shown in Figure 16. The Byte_Program command sets up the byte for programming. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first and begins the program operation. The end of program can be detected using either the Data# Polling, Toggle bit, or Successive reads. Reset Operation The Reset command is provided as a means to safely abort the erase or program command s equences. Following either setup commands (erase or program) with a write of FFH will safely abort the operation. Memory contents will not be altered. After the Reset command, the device er turns to the read mode. The Reset command does not enable software data protection. See Figure 7 for timing waveforms.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.3
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Read The Read operation is initiated by setting CE#, and OE# to logic low and setting WE# to logic high (See Table 2). See Figure 4 for read memory timing waveform. The read operation from the host retrieves data from the array. The device er mains enabled for read until another operation mode is accessed. During initial power-up, the device is in the read mode and is software data protected. The device must be unprotected to execute a write command. The read operation of the 28LF040 is controlled by OE# and CE# at logic low. When CE # is high, the chip is deselected and only standby power will be consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when CE# and OE# are high. Read_ID operation The Read_ID operation is initiated by writing a single command (90H). A read of address 0000H will output the manufacturer's code (BFH). A read of address 0001H will output the device code (04H). Any other valid command will terminate this operation. Data Protection In order to protect the integrity of nonvolatile data storage, the 28LF040 provides both hardware and software features to prevent inadvertent writes to the device, for example, during system power-up or power-down. Such provisions are described below. Hardware Data Protection The 28LF040 is designed with hardware features to prevent inadvertent writes. This is done in the following ways: 1. Write Inhibit Mode: OE# low, CE#, or WE# high will inhibit the write oper ation. 2. Noise/Glitch Protection: A WE# pulse width of less than 15 ns will not initiate a write c ycle. 3. VCC Power Up/Down Detection: The write o peration is inhibited when V is less than CC 2.5V. 4. After power-up the device is in the read mode and the device is in the software data protect state. Software Data Protection (SDP) The 28LF040 has software methods to further prevent inadvertent writes. In order to perform an erase or program operation, a two-step command sequence consisting of a set-up command fo llowed by an execute command avoids inadvertent erasing and programming of the d evice. The 28LF040 will default to software data prote ction after power up. A sequence of seven consecutive reads at specific addresses will u nprotect the device The address sequence is 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The address bus is latched on the rising edge of OE# or CE#, whichever occurs first. A similar seven read sequence of 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect the device. Also refer to Figures 10 and 11 for the 7 read cycle sequence Software Data Protection. The I/O pins can be in any state (i.e., high, low, or tristate). Write Operation Status Detection The 28LF040 provides three means to detect the completion of a write cycle, in order to optimize the system write cycle time. The end of a write cycle (erase or program) can be detected by three means: 1) monitoring the Data# Polling bit; 2) monitoring the Toggle bit; or 3) by two successive read of the same data. These three detection mechanisms are described below. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simult a neous with the completion of the write cycle. If this occurs, the system may possibly get an err o neous result, i.e., valid data may appear to conflict with the DQ used. In order to prevent spurious rejection, if an erroneous result occurs, the soft ware routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has co mpleted the write cycle, otherwise the rejection is valid.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.4
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Data# Polling (DQ 7) The 28LF040 features Data# Polling to indicate the write operation status. During a write oper a tion, any attempt to read the last byte loaded during the byte-load cycle will receive the co mplement of the true data on DQ . Once the write 7 cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 12 for Data Polling timing waveforms. In order for Data# Polling to function correctly , the byte being polled must be erased prior to pr o gramming. Toggle Bit ( DQ 6) An alternative means for determining the write operation status is by monitoring the Toggle Bit, DQ6. During a write operation, consecutive a ttempts to read data from the device will result in DQ6 toggling between logic 0 (low) and logic 1 (high). When the write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 13 for Toggle Bit ti ming waveforms. Successive Reads An Alternative means for determining an end of a write cycle is by reading the same address for two consecutive data matches. Product Identification The Product Identification mode identifies the d evice as 28LF040 and the manufacturer as SST. This mode may be accessed by hardware and software operations. The hardware operation is typically used by an external programmer to identify the correct algorithm for the 28LF040. U sers may wish to use the software operation to identify the device (i.e., using the device code). For details see Table 2 for the hardware operation and Figure 19 for the software operation. The manufacturer and device codes are the same for both operations. Product Identification Table Byte Manufacturer Code Device Code 0000 H 0001 H Data BF H 04 H
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.5
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
4,194,304 Bit X-Decoder EEPROM Cell Array
A18-A0
Address buffer & Latches Y-Decoder
CEH# OE# WE# DQ7 - DQ0 Control Logic I/O Buffers and Data Latches
Figure 1:
Functional Block Diagram of SST 28LF040
Pin #1 indicator
N/C N/C A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 N/C N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Standard Pinout Top View
Die up
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
N/C N/C OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 N/C N/C
Figure 2A:
Standard Pin Assignments for 4 0-pin TSOP Pac kages
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.6
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard Pinout Top View
Die up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
Figure 2B:
Standard Pin Assignments for 32-pin TSOP Packages
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 23 22 21 20 19 18 17
Vcc WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 DQ1 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 4 A12
A15 A16
A18 Vcc
WE# A17
3
2
1
32 31 30 29 28 27 26 A14 A13 A8 A9 A11 OE# A10 CE# DQ7
32-Pin PDIP
Top View 24
32-Lead PLCC Top View
25 24 23 22 21
14 15 16
17 18 19
20
DQ2
Vss DQ4 DQ6 DQ3 DQ5
Figure 3: Pin Assignments for 32-pin Plastic DIPs and 32-pin PLCCs
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.7
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Table 1: Symbol A18 -A8 A7-A0 DQ7-DQ0 Pin Description Pin Name Row Address Inputs Column Address Inputs Data Input/Output
CE# OE# WE# Vcc Vss Note:
(1)
Chip Enable Output Enable Write Enable Power Supply Ground
Functions To provide memory addresses. Row addresses define a sector. Selects the byte within the sector. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE#, CE # is high. To activate the device when CE # is low.(1) To gate the data output buffers. (1) To control the write operations. (1) To provide 3.3-volt supply ( 0.3 V)
This pin is considered an input for the purposes of the DC Operation Characteristics Table.
Table 2: Mode
Operation Modes Selection CE# OE# VIL VIL VIL VIH X X VIL VIL VIL VIH VIH X VIL X VIH VIL
WE# VIH VIL VIL X X VIH VIL VIH
DQ DOUT DIN DIN High Z High Z/ DOUT High Z/ DOUT DIN
Address AIN AIN, See Table 3 AIN, See Table 3 X X X See Table 3
Read Byte Program Sector Erase Standby Write Inhibit Write Inhibit Software Chip Erase Product Identification Hardware Mode
Software Mode SDP Enable & Disable Mode Reset
VIL VIL VIL
VIH VIH VIH
VIL VIL VIL
Manufacturer A18 -A1=VIL, A9=VH, A0=V IL Code (BF) Device Code (04) A18 -A1=VIL, A9=VH, A0=V IH See Table 3 See Table 3 See Table 3
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.8
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Table 3:
Software Command Summary
Required Cycle(s) Setup Command Cycle Type (1) Addr (2,3 Data (4)
)
Command Su mmary
Execute Command C ycle Type (1) Addr (2,3 Data (4)
)
SDP (5)
Sector_Erase Byte_Program Chip_Erase Reset Read_ID Software_Data_Protect Software_Data_Unprotect Notes:
2 2 2 1 3 7 7
W W W W W R R
X X X X X (6) (7)
20H 10H 30H FFH 90H
W W W R
SA PA X (8)
D0H PD 30H (8)
N N N Y Y
1. Type definition: W = Write, R = Read, X= don't care 2. Addr (Address) definition: SA = Sector Address = A - A8, sector size = 256 bytes; A - A0 = X for this 18 7 command. 3. Addr (Address) definition: PA = Program Address = A - A0. 18 4. Data definition: PD = Program Data, H = number in hex. 5. SDP = Software Data Protect mode using 7 Read CycleSequence. a) Y = the operation can be executed with protection enabled b) N = the operation cannot be executed with protection enabled 6. Refer to Figure 11 for the 7 Read Cycle sequence for Software_Data_Protect. 7. Refer to Figure 10 for the 7 Read Cycle sequence for Software_Data_Unprotect. 8. Address 0000H retrieves the manufacturer' code of BFH and address 0001H retrieves the device code of 04H.
Table 4: Memory Array Detail Sector Select A18 - A8
Byte Select A7 - A0
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.9
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the po erational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ........................................................................ -55C to +125C Storage Temperature ............................................................................. -65C to +150C D. C. Voltage on Any Pin to Ground Potential ........................................ -0.5V to VCC + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ................... -1.0V to VCC + 1.0V Voltage on A9 Pin to Ground Potential .................................................... -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25C) ................................. 1.0W Through Soldering Temper ature (10 Seconds)......................................... 300C Surface Mount Lead Soldering Temperature (3 Seconds) ...................... 240C (1) Output Short Circuit Current ................................................................. 100 mA Note:
(1)
Outputs shorted for no more than one second. No more than one output shorted at a time. Operating Range
Ambient Temp 0 C to +70 C -40 C to +85 C VCC 3.0V to 3.6V 3.0V to 3.6V
Table 5:
Range Commercial Industrial
Table 6:
AC Conditions of Test
Input Rise/Fall Time...............10 ns Output Load...........................1 TTL Gate and CL = 100 pF See Figures 14 and 15
Table 7: DC Operating Characteristics Symbo Parameter Limits l Min Max ICC Power Supply Current Read Program and Erase ISB1 ISB2 ILI ILO VIL VIH VOL VOH VH IH Standby VCC Current (TTL input) Standby VCC Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Supervoltage for A9 Supervoltage Current for A 9 10 25 1 20 1 10 0.8 2.0 0.4 2.4 11.6 12.4 200
Units Test Conditions
mA mA mA A A A V V V V V A
CE# = OE# =VIL, WE# =VIH , all I/Os open Address input = VIL/VIH, at f=1/TRC Min. VCC = VCC Max CE# =WE# =VIL, OE# =VIH VCC =VCC Max. CE# =OE# =WE# = VIH , VCC =VCC Max CE# = OE# = WE# = VCC -0.3V, VCC =VCC Max VIN = GND to VCC, VCC = VCC Max. VOUT =GND to VCC, VCC = VCC Max. VCC = VCC Max. VCC = VCC Max. IOL = 100 A, VCC = VCC Min. IOH = -100 A, VCC = VCC Min. CE#=OE#=VIL, WE#=VIH CE#=OE#=VIL, WE#=VIH, A9 = VH Max.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.10
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Table 8: Power-up Timings Symbol Parameter (1) TPU-READ Power-up to Read Operation TPU-WRITE (1) Power-up to Write Operation
Maximum 10 10
Units ms ms
Table 9: Capacitance (Ta = 25 C, f=1 Mhz, other pins open) Parameter Description Test Condition (1) CI/O I/O Pin Capacitance VI/O = 0V CIN (1)
(1)
Maximum 12 pF 6 pF
Input Capacitance
VIN = 0v
Note:
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 10: Reliability Characteristics Symbol Parameter NEND TDR (1) VZAP_HBM (1) VZAP_MM (1) ILTH (1) Note:
(1)
Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up
Minimum Specification 1,000 & 10,000(2) 100 1000 200 100
Units Cycles Years Volts Volts mA
Test Method MIL-STD-883, Method 1033 MIL-STD-883, Method 1008 MIL-STD-883, Method 3015 JEDEC Standard A115 JEDEC Standard 17
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. See Ordering Information for desired type.
(2)
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.11
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
AC Characteristics Table 11: Read Cycle Timing Parameters IEEE Industry Symbol Symbol Parameter tAVAV TRC Read Cycle time tAVQV TAA Address Access Time tELQV TCE Chip Enable Access Time tGLQV TOE Output Enable Access Time tEHQZ TCLZ(1) CE# Low to Active Output (1) tGHQZ TOLZ OE# Low to Active Output tELQX TCHZ (1) CE# High to High-Z Output tGLQX TOHZ (1) OE# High to High-Z Output (1) tAXQX TOH Output Hold from Address Change 28LF040-200 Min Max 200 200 200 120 0 0 60 60 0 28LF040-250 Min Max 250 250 250 120 0 0 60 60 0
Units ns ns ns ns ns ns ns ns ns
Table 12: IEEE Symbol tAVA tWLWH tAVWL tWLAX tELWL tWHEX tGHWL tWGL tWLEH tDVWH tWHDX tWHWL2 tWHWL3 tEHEL tWHWL1
Erase/Program Cycle Timing Parameters Industry Symbol Parameter TBP Byte Program Cycle Time TWP Write Pulse Width (WE#) TAS Address Setup Time TAH Address Hold Time TCS CE# Setup Time TCH CE# Hold Time TOES OE# High Setup Time TOEH OE# High Hold Time TCP Write Pulse Width (CE#) TDS Data Setup Time TDH Data Hold Time TSE Sector Erase Cycle Time (1) TRST Reset Command Recovery Time TSCE Software Chip_Erase Cycle Time TCPH CE# High Pulse Width TWPH WE# High Pulse Width TPCP (1) Protect Chip Enable Pulse Width (1) TPCH Protect Chip Enable High Time (1) TPAS Protect Address Setup Time TPAH (1) Protect Address Hold Time
Min 200 10 100 0 0 20 20 200 100 20
Max 40
Units s ns ns ns ns ns ns ns ns ns ns ms s ms ns ns ns ns ns ns
4 4 20 50 50 20 20 0 100
Note:
(1)
This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.12
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Figure 4:
Read Cycle Timing Diagram
Figure 5:
WE# Controlled Byte Program Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.13
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Figure 6:
CE# Controlled Byte Program Timing Diagram
Figure 7:
Reset Command Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.14
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Figure 8:
Chip_Erase Timing Diagram
Figure 9:
Sector Erase Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.15
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Figure 10:
Software Data Unprotect Timing Diagram
Figure 11:
Software Data Protect Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.16
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Figure 12:
Data# Polling Timing Diagram
Figure 13:
Toggle Bit Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.17
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
2.4 INPUT
2.0 REFERENCE POINTS 0.8
2.0 OUTPUT 0.8
0.4
AC test inputs are driven at V (2.4 VTTL ) for a logic "1" and VOL (0.4 VTTL ) for a logic "0". MeasureOH ment reference points for inputs and outputs are V (2.0 VTTL ) and VIL (0.8 VTTL ). Inputs rise and fall IH times (10% 90%) are <10 ns.
Figure 14:
AC Input/Output Reference Wav eform
TEST LOAD EXAMPLE
VCC
TO TESTER
RL
HIGH
TO DUT
CL
RL
LOW
Figure 15:
Test Load Example
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.18
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Figure 16:
Byte Program Flowchart
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.19
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Internal Timer
Byte Program/ Sector Erase Initiated
Toggle Bit
Byte Program/ Sector Erase Initiated
Data # Polling
Byte Program Initiated
Wait TBP or TSE
Read byte
Read DQ7
Write Completed
Read same byte
No
Is DQ7 = true data?
Yes No Does DQ6 match ? Write Completed
Yes Write Completed Figure 17: Write Wait Options
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.20
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Figure 18:
Sector_Erase Flowchart
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.21
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Execute Read_ID Command (90H) To enter ID mode
Read Address 0000H MFG's Code = SST (BF)
Read Address 0001H Device Code = 28LF040 (04)
Execute Reset Command (FFH) to exit from mode
Figure 19:
Software Product ID Flow
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
12.22
SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Product Ordering Information
Device SST28LF040 -
Speed XXX -
Suffix1 XX -
Suffix2 XX
Package Modifier I =40 leads H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC E = TSOP (die up) U = Unencapsulated die Operating Temperature C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 3 = 1000 cycles 4 = 10,000 cycles Read Access Speed 200 = 200 ns 250 = 250 ns
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
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SST 28LF040 3.0V-only 4 Megabit SuperFlash EEPROM
Valid combinations SST28LF040-200-4C- EH SST28LF040-200-4C- PH SST28LF040-250-4C- EH SST28LF040-250-4C- PH SST28LF040-200-3C- EH SST28LF040-200-3C- PH SST28LF040-250-3C- EH SST28LF040-250-3C- PH SST28LF040-200-4I- EH SST28LF040-250-4I- EH
Example:
SST28LF040-200-4C- EI SST28LF040-250-4C- EI SST28LF040-250-4C- U1 SST28LF040-200-3C- EI SST28LF040-250-3C- EI SST28LF040-250-3C- U1 SST28LF040-200-4I- EI SST28LF040-250-4I- EI
SST28LF040-200-4C- NH SST28LF040-250-4C- NH
SST28LF040-200-3C- NH SST28LF040-250-3C- NH
SST28LF040-200-4I- NH SST28LF040-250-4I- NH
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales re presentative to confirm availability of valid combinations and to determine availability of new co mbinations.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
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